As the market for communications devices increases, so also does the market for associated electronic components. Examples of such components include phase-locked loops (PLL) and transceivers. Such components generate frequency signals necessary for the operation of the communications devices, and may often be required to switch between frequencies. However, as the market for such components increases, so also does the demand for higher performance of these components. As an example, a given PLL or transceiver often does not settle on a switched frequency immediately. As a result, the given PLL or transceiver may have a performance demand in the form of a reduced settling or lock time in generating the frequency signals or switching from one frequency to another.
Due to the increasing demand for higher performance of the associated electronic components of communications devices, such as PLLs and transceivers, manufacturers of such components may want to not only ensure that a given PLL or transceiver meets or exceeds the settling or lock time specification, but that the testing of such specification is performed efficiently. Typically, when testing a settling or lock time, a given device-under-test (DUT) is activated to generate an output signal, and the output signal is down-converted to an intermediate frequency. The intermediate frequency can then be captured by a digitizer, and a settled frequency error can be calculated by averaging zero-crossings over a burst of signals within a specified frequency. The settling or lock time can then be determined from the frequency error.
The method of averaging zero-crossings over a burst of signals, however, can lead to sampling errors through uncertainties of time quantization. Additionally, by averaging a number of periods of signal bursts, the zero-crossing method of determining the settling or lock time of a DUT can be inaccurate. Such uncertainties and inaccuracies can lead to acceptance of bad components and/or rejection of good components. To increase the accuracy of zero-crossing testing of a component, the intermediate frequency can be decreased. However, this may result in a longer testing time necessary for data capture.